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1 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation features fast 20mbps differential transmission rates internal transceiver termination resistors for v.11 & v.35 interface modes: ? rs-232 (v.28) ? eia-530 (v.10 & v.11) ? x.21 (v.11) ? eia-530a (v.10 & v.11) ? rs-449/v.36 ? v.35 (v.35 & v.28) (v.10 & v.11) protocols are software selectable with 3-bit word eight (8) drivers and eight (8) receivers termination network disable option internal line or digital loopback for diagnostic testing adheres to net1/net2 and tbr-2 compliancy requirements easy flow-through pinout +3.3v only operation individual driver and receiver enable/disable controls operates in either dte or dce mode SP3508 rugged 3.3v, 20mbps, 8 channel multiprotocol transceiver with programmable dce/dte and termination resistors description the SP3508 is a monolithic device that supports eight (8) popular serial interface standards for wide area network (wan) connectivity. the SP3508 is fabricated using a low power bicmos process technology, and incorporates a sipex regulated charge pump allowing +3.3v only operation. sipex's patented charge pump provides a regulated output of +5.5v, which will provide enough voltage for compliant operation in all modes. eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. the SP3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. all necessary termination is integrated within the SP3508 and is switchable when v.35 drivers and v.35 receivers, or when v.11 receivers are used. the SP3508 provides the controls and transceiver availability for operating as either a dte or dce. additional features with the SP3508 include internal loopback that can be initiated in any of the operating modes by use of the loopback pin. while in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. the SP3508 also includes a latch enable pin with the driver and receiver address decoder. the internal v.11 or v.35 termination can be switched off using a control pin (term_off) for monitoring applications. all eight (8) drivers and receivers in the SP3508 include separate enable pins for added convenience. the SP3508 is ideal for wan serial ports in networking equipment such as routers, access concentrators, network muxes, dsu/csu's, networking test equipment, and other access devices. applicable u.s. patents-5,306,954; and others patents pending ? preliminary applications router frame relay csu dsu pbx secure communication terminals now available in lead free packaging refer to page 9 for pinout
2 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation electrical specifications t a = 0 to 70 c and v cc = 3.3v 5% unless otherwise noted. the ? denotes the specifications which apply over the full operating temperature range (-40 c to +85 c) , unless otherwise specified. v cc ................................................................................................ +7v input voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers ............................................. -0.3v to (v cc +0.5v) receivers ........................................................... 15.5v output voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers ................................................................... 12v receivers ........................................ -0.3v to (v cc +0.5v) storage temperature ................................................ -65 c to +150 c power dissipation ................................................................. 1520mw (derate 19.0mw/ c above +70 c) due to the relatively large package size of the 100-pin quad flat- pack, storage in a low humidity environment is preferred. large high density plastic packages are moisture sensitive and should be stored in dry vapor barrier bags. prior to usage, the parts should remain bagged and stored below 40 c and 60%rh. if the parts are removed from the bag, they should be used within package derating: ? ja ................................................................................................................. 36.9 c/w ? jc .................................................................................................................... 6.5 c/w these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. absolute maximum ratings 48 hours or stored in an environment at or below 20%rh. if the above conditions cannot be followed, the parts should be baked for four hours at 125 c in order to remove moisture prior to soldering. sipex ships the 100-pin lqfp in dry vapor barrier bags with a humidity indicator card and desiccant pack. the humidity indicator should be below 30%rh. storage considerations r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s t u p n i c i g o l v l i 8 . 0 ? ? ? ? ? v v h i 0 . 2 ? ? ? ? ? v s t u p t u o c i g o l v l o 4 . 0 ? ? ? ? ? va m 2 . 3 ? = t u o i v h o v c c - 6 . 0 v c c - 3 . 0 ? ? ? ? ? v a m 0 . 1 = t u o i ) s t u p t u o ( s r e t e m a r a p c d r e v i r d 8 2 . v s t u p t u o e g a t l o v t i u c r i c n e p o5 1 ? ? ? ? ? v1 e r u g i f r e p e g a t l o v d e d a o l0 . 5 5 1 ? ? ? ? ? v2 e r u g i f r e p t n e r r u c t i u c r i c - t r o h s0 0 1 ? ? ? ? ? a m4 e r u g i f r e p e c n a d e p m i f f o - r e w o p0 0 3 ? ? ? ? ?? 5 e r u g i f r e p ) s t u p t u o ( s r e t e m a r a p c a r e v i r d 8 2 . v v c c s r e t e m a r a p c a r o f v 3 . 3 + = e m i t n o i t i s n a r t5 . 1 ? ? ? ? ? s v 3 - o t v 3 + , 6 e r u g i f r e p e t a r w e l s s u o e n a t n a t s n i0 3s / v3 e r u g i f r e p t : y a l e d n o i t a g a p o r p l h p 5 . 00 . 10 . 3 ? ? ? ? ? s t : y a l e d n o i t a g a p o r p h l p 5 . 00 . 10 . 3 ? ? ? ? ? s e t a r n o i s s i m s n a r t . x a m0 2 10 3 2 ? ? ? ? ? s p b k
3 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation electrical specifications t a = 0 to 70 c and v cc = 3.3v 5% unless otherwise noted. the ! denotes the specifications which apply over the full operating temperature range (-40 c to +85 c) , unless otherwise specified. r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c ) s t u p n i ( s r e t e m a r a p c d r e v i e c e r 8 2 . v e c n a d e p m i t u p n i37 k 7 e r u g i f r e p s a i b t i u c r i c - n e p o0 . 2 + v8 e r u g i f r e p d l o h s e r h t h g i h7 . 10 . 3 v d l o h s e r h t w o l8 . 02 . 1 v s r e t e m a r a p c a r e v i e c e r 8 2 . v v c c s r e t e m a r a p c a r o f v 3 . 3 + = t : y a l e d n o i t a g a p o r p l h p 0 0 10 0 5s n t : y a l e d n o i t a g a p o r p h l p 0 0 10 0 5s n e t a r n o i s s i m s n a r t x a m0 2 15 3 2s p b k ) s t u p t u o ( s r e t e m a r a p c d r e v i r d 0 1 . v e g a t l o v t i u c r i c n e p o0 . 4 0 . 6 v9 e r u g i f r e p e g a t l o v d e t a n i m r e t - t s e tv 9 . 0 c o v0 1 e r u g i f r e p t n e r r u c t i u c r i c - t r o h s0 5 1 a m1 1 e r u g i f r e p t n e r r u c f f o - r e w o p0 0 1 a 2 1 e r u g i f r e p ) s t u p t u o ( s r e t e m a r a p c a r e v i r d 0 1 . v v c c s r e t e m a r a p c a r o f v 3 . 3 + = e m i t n o i t i s n a r t0 0 2 s n% 0 9 o t % 0 1 ; 3 1 e r u g i f r e p t : y a l e d n o i t a g a p o r p l h p 0 0 10 0 5 s n t : y a l e d n o i t a g a p o r p h l p 0 0 10 0 5 s n e t a r n o i s s i m s n a r t x a m0 2 1 s p b k ) s t u p n i ( s r e t e m a r a p c d r e v i e c e r 0 1 . v t n e r r u c t u p n i5 2 . 3 -5 2 . 3 +a m5 1 d n a 4 1 s e r u g i f r e p e c n a d e p m i t u p n i4 k y t i v i t i s n e s3 . 0 v s r e t e m a r a p c a r e v i e c e r 0 1 . v v c c s r e t e m a r a p c a r o f v 3 . 3 + = t : y a l e d n o i t a g a p o r p l h p 0 2 10 5 2 s n t : y a l e d n o i t a g a p o r p h l p 0 2 10 5 2 s n e t a r n o i s s i m s n a r t x a m0 2 1 s p b k
4 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation electrical specifications t a = 0 to 70 c and v cc = 3.3v 5% unless otherwise noted. the ! denotes the specifications which apply over the full operating temperature range (-40 c to +85 c) , unless otherwise specified. r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c ) s t u p t u o ( s r e t e m a r a p c d r e v i r d 1 1 . v v ( e g a t l o v t i u c r i c n e p o c o )0 . 6 v6 1 e r u g i f r e p e g a t l o v d e t a n i m r e t t s e t0 . 2 v7 1 e r u g i f r e p 5 . 0v ( c o ) v e c n a l a b4 . 0 v 7 1 e r u g i f r e p t e s f f o0 . 3 + v7 1 e r u g i f r e p t n e r r u c t i u c r i c - t r o h s0 5 1 a m8 1 e r u g i f r e p t n e r r u c f f o - r e w o p0 0 1 a 9 1 e r u g i f r e p ) s t u p t u o ( s r e t e m a r a p c a r e v i r d 1 1 . v v c c s r e t e m a r a p c a r o f v 3 . 3 + = e m i t n o i t i s n a r t0 1 s n o t % 0 1 ; 5 3 d n a 1 2 s e r u g i f r e p ; f p 0 5 = l c g n i s u % 0 9 t : y a l e d n o i t a g a p o r p l h p 0 30 6 s n5 3 d n a 2 3 s e r u g i f r e p t : y a l e d n o i t a g a p o r p h l p 0 30 6 s n5 3 d n a 2 3 s e r u g i f r e p w e k s l a i t n e r e f f i d50 1 s n5 3 d n a 2 3 s e r u g i f r e p e t a r n o i s s i m s n a r t . x a m0 2 s p b m ) s t u p n i ( s r e t e m a r a p c d r e v i e c e r 1 1 . v e g n a r e d o m n o m m o c7 -7 + v y t i v i t i s n e s2 . 0 v t n e r r u c t u p n i5 2 . 3 -5 2 . 3 a m r o n o r e w o p ; 2 2 d n a 0 2 e r u g i f r e p f f o ? 0 0 1 / w t n e r r u c n o i t a n i m r e t - 7 . 0 6 5 a m 4 2 d n a 3 2 e r u g i f r e p e c n a d e p m i t u p n i4 k s r e t e m a r a p c a r e v i e c e r 1 1 . v v c c s r e t e m a r a p c a r o f v 3 . 3 + = f p 0 5 = l c g n i s u t : y a l e d n o i t a g a p o r p l h p 0 30 6s n7 3 d n a 2 3 s e r u g i f r e p t : y a l e d n o i t a g a p o r p h l p 0 30 6s n7 3 d n a 2 3 s e r u g i f r e p w e k s50 1s n2 3 e r u g i f r e p e t a r n o i s s i m s n a r t x a m0 2s p b m
5 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation electrical specifications t a = 0 to 70 c and v cc = 3.3v 5% unless otherwise noted. the ! denotes the specifications which apply over the full operating temperature range (-40 c to +85 c) , unless otherwise specified. r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c ) s t u p t u o ( s r e t e m a r a p c d r e v i r d 5 3 . v e g a t l o v t i u c r i c n e p o0 2 . 1 v 6 1 e r u g i f r e p e g a t l o v d e t a n i m r e t t s e t4 4 . 0 6 6 . 0 v 5 2 e r u g i f r e p t e s f f o6 . 0 v5 2 e r u g i f r e p t o o h s r e v o t u p t u o- v 2 . 0 - t s - 2 . 0 + v t s v v ; 5 2 e r u g i f r e p t s e t a t s y d a e t s = e u l a v e c n a d e p m i e c r u o s0 50 5 1 z ; 6 2 e r u g i f r e p s v = 2 v / 1 0 5 x e c n a d e p m i t i u c r i c - t r o h s5 3 15 6 1 7 2 e r u g i f r e p ) s t u p t u o ( s r e t e m a r a p c a r e v i r d 5 3 . v v c c s r e t e m a r a p c a r o f v 3 . 3 + = e m i t n o i t i s n a r t0 2 s n t : y a l e d n o i t a g a p o r p l h p 0 30 6 s nc ; 5 3 d n a 2 3 s e r u g i f r e p l f p 0 2 = t : y a l e d n o i t a g a p o r p h l p 0 30 6 s nc ; 5 3 d n a 2 3 s e r u g i f r e p l f p 0 2 = w e k s l a i t n e r e f f i d5 s nc ; 5 3 d n a 2 3 s e r u g i f r e p l f p 0 2 = e t a r n o i s s i m s n a r t . x a m0 2 s p b m ) s t u p n i ( s r e t e m a r a p c d r e v i e c e r 5 3 . v y t i v i t i s n e s0 5 0 0 2 v m e c n a d e p m i e c r u o s0 90 1 1 z ; 9 2 e r u g i f r e p s v = 2 v / 1 0 5 x e c n a d e p m i t i u c r i c - t r o h s5 3 15 6 1 0 3 e r u g i f r e p s r e t e m a r a p c a r e v i e c e r 5 3 . v v c c s r e t e m a r a p c a r o f v 5 + = t : y a l e d n o i t a g a p o r p l h p 0 30 6s nc ; 7 3 d n a 2 3 s e r u g i f r e p l f p 0 2 = t : y a l e d n o i t a g a p o r p h l p 0 30 6s nc ; 7 3 d n a 2 3 s e r u g i f r e p l f p 0 2 = w e k s50 1s nc ; 2 3 s e r u g i f r e p l f p 0 2 = e t a r n o i s s i m s n a r t . x a m0 2s p b m s t n e r r u c e g a k a e l r e v i e c s n a r t t n e r r u c e t a t s - 3 t u p t u o r e v i r d0 0 2a d e l b a s i d s r e v i r d ; 1 3 e r u g i f r e p e t a t s - 3 t u p t u o r e v i e c e r t n e r r u c 10 1 a d x 1 1 1 =
6 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation electrical specifications t a = 0 to 70 c and v cc = 3.3v 5% unless otherwise noted. the ! denotes the specifications which apply over the full operating temperature range (-40 c to +85 c) , unless otherwise specified. r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s t n e m e r i u q e r r e w o p v c c 5 1 . 33 . 35 4 . 3v i c c ) d e t c e l e s e d o m o n (1 a i l l a c c v h t i w e r a s e u l a v c c v 3 . 3 + = ) 2 3 2 - s r / 8 2 . v5 9 a m f n i & e v i t c a s r e v i r d ; s p b k 0 3 2 = d e d a o l ) 2 2 4 - s r / 1 1 . v (0 3 2 a mf n i d e d a o l & e v i t c a s r e v i r d ; s p b m 0 2 = ) 9 4 4 - s r & 0 3 5 - a i e (0 7 2 a mf n i d e d a o l & e v i t c a s r e v i r d ; s p b m 0 2 = ) 5 3 . v (0 7 1 a m i f @ 5 3 . v n @ 8 2 . v , s p b m 0 2 = s p b k 0 3 2
7 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation other ac characteristics t a = 0 to 70 c and v cc = +3.3v unless otherwise noted. parameter min. typ. max. units conditions driver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.70 5.0 sc l = 100pf, fig. 33 & 39 ; s 1 closed t pzh ; tri-state to output high 0.40 2.0 sc l = 100pf, fig. 33 & 39 ; s 2 closed t plz ; output low to tri-state 0.20 2.0 sc l = 100pf, fig. 33 & 39 ; s 1 closed t phz ; output high to tri-state 0.40 2.0 sc l = 100pf, fig. 33 & 39 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.15 2.0 sc l = 100pf, fig. 33 & 39 ; s 1 closed t pzh ; tri-state to output high 0.20 2.0 sc l = 100pf, fig. 33 & 39 ; s 2 closed t plz ; output low to tri-state 0.20 2.0 sc l = 100pf, fig. 33 & 39 ; s 1 closed t phz ; output high to tri-state 0.15 2.0 sc l = 100pf, fig. 33 & 39 ; s 2 closed rs-422/v.11 t pzl ; tri-state to output low 2.80 10.0 sc l = 100pf, fig. 33 & 36 ; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 33 & 36 ; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 33 & 36 ; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 33 & 36 ; s 2 closed v.35 t pzl ; tri-state to output low 2.60 10.0 sc l = 100pf, fig. 33 & 36 ; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 33 & 36 ; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 33 & 36 ; s 1 closed t phz ; output high to tri-state 0.15 2.0 sc l = 15pf, fig. 33 & 36 ; s 2 closed receiver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.12 2.0 sc l = 100pf, fig. 34 & 37 ; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 100pf, fig. 34 & 37 ; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 100pf, fig. 34 & 37 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.10 2.0 sc l = 100pf, fig. 34 & 37 ; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 100pf, fig. 34 & 37 ; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 100pf, fig. 34 & 37 ; s 2 closed
8 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation other ac characteristics: continued t a = 0 to 70 c and v cc = +3.3v unless otherwise noted. parameter min. typ. max. units conditions rs-422/v.11 t pzl ; tri-state to output low 0.10 2.0 sc l = 100pf, fig. 34 & 38 ; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 34 & 38 ; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 34 & 38 ; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 34 & 38 ; s 2 closed v.35 t pzl ; tri-state to output low 0.10 2.0 sc l = 100pf, fig. 34 & 38 ; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 34 & 38 ; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 34 & 38 ; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 34 & 38 ; s 2 closed transceiver to transceiver skew (per figures 32, 35, 37) rs-232 driver 100 ns [ (t phl ) tx1 ? (t phl ) txn ] 100 ns [ (t plh ) tx1 ? (t plh ) txn ] rs-232 receiver 20 ns [ (t phl ) rx1 ? (t phl ) rxn ] 20 ns [ (t phl ) rx1 ? (t phl ) rxn ] rs-422 driver 2 ns [ (t phl ) tx1 ? (t phl ) txn ] 2ns[ (t plh ) tx1 ? (t plh ) txn ] rs-422 receiver 3 ns [ (t phl ) rx1 ? (t phl ) rxn ] 3ns[ (t phl ) rx1 ? (t phl ) rxn ] rs-423 driver 5 ns [ (t phl ) tx2 ? (t phl ) txn ] 5ns[ (t plh ) tx2 ? (t plh ) txn ] rs-423 receiver 5 ns [ (t phl ) rx2 ? (t phl ) rxn ] 5ns[ (t phl ) rx2 ? (t phl ) rxn ] v.35 driver 4 ns [ (t phl ) tx1 ? (t phl ) txn ] 4ns[ (t plh ) tx1 ? (t plh ) txn ] v.35 receiver 6 ns [ (t phl ) rx1 ? (t phl ) rxn ] 6ns[ (t phl ) rx1 ? (t phl ) rxn ]
9 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation pinout gnd 1 sden 2 tten 3 sten 4 rsen 5 tren 6 rrcen 7 rlen 8 llen 9 rden 10 r ten 11 txcen 12 csen13 dmen 14 rrten 15 icen 16 tmen 17 d0 18 d1 19 d2 20 d_latch 21 term_off 22 vcc 23 c3p 24 gnd 25 c3n 26 vss2 27 agnd 28 a vcc 29 loopback 30 txd 31 txce 32 st 33 r ts 34 dtr 35 dcd_dce 36 rl 37 ll 38 rxd 39 rxc 40 txc 41 cts 42 dsr 43 dcd_dte 44 ri 45 tm 46 gnd 47 vcc 48 rd(b) 49 rd(a) 50 75 gnd 74 c1p 73 vcc 72 c2p 71 gnd 70 c1n 69 c2n 68 vss1 67 rl(a) 66 vcc 65 ll(a) 64 tm(a) 63 ic 62 rrt(a) 61 rrt(b) 60 gndv10 59 dm(a) 58 dm(b) 57 cs(a) 56 cs(b) 55 txc(a) 54 gnd 53 txc(b) 52 rt(a) 51 rt(b) 100 vcc 99 sd(b) 98 vcc 97 sd(a) 96 gnd 95 tt(b) 94 vcc 93 tt(a) 92 gnd 91 st(b) 90 vcc 89 st(a) 88 gnd 87 tr(b) 86 vcc 85 tr(a) 84 gnd 83 rs(b) 82 vcc 81 rs(a) 80 gnd 79 rrc(a) 78 vcc 77 rcc(b) 76 vdd SP3508 ?
10 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation SP3508 pin designation pin number pin name description pin number pin name description 1 gnd signal ground 51 rt(b) rxc non-inverting input 2 sden txd driver enable input 52 rt(a) rxc inverting input 3 tten txce driver enable input 53 txc(b) txc non-inverting input 4 sten st driver enable input 54 gnd signal ground 5 rsen rts driver enable input 55 txc(a) txc inverting input 6 tren dtr driver enable input 56 cs(b) cts non-inverting input 7 rrcen dcd driver enable input 57 cs(a) cts inverting input 8 rlen rl driver enable input 58 dm(b) dsr non-inverting input 9 llen ll driver enable input 59 dm(a) dsr inverting input 10 rden rxd receiver enable input 60 gndv10 v.10 rx reference node 11 rten rxc receiver enable input 61 rrt(b) dcd dte non-inverting input 12 txcen txc receiver enable input 62 rrt(a) dcd dte inverting input 13 csen cts receiver enable input 63 ic ri receiver input 14 dmen dsr receiver enable input 64 tm(a) tm receiver input 15 rrten dcd dte receiver enable input 65 ll(a) ll driver output 16 icen ri receiver enable input 66 vcc power supply input 17 tmen tm receiver enable input 67 rl(a) rl driver output 18 d0 mode select input 68 vss1 -2xvcc charge pump output 19 d1 mode select input 69 c2n charge pump capacitor 20 d2 mode select input 70 c1n charge pump capacitor 21 d_latch decoder latch input 71 gnd signal ground 22 term_off termination disable input 72 c2p charge pump capacitor 23 vcc power supply input 73 vcc power supply input 24 c3p charge pump capacitor 74 c1p charge pump capacitor 25 gnd signal ground 75 gnd signal ground 26 c3n charge pump capacitor 76 vdd 2xvcc charge pump output 27 vss2 minus vcc 77 rrc(b) dcd dce non-inverting output 28 agnd signal ground 78 vcc power supply input 29 avcc power supply input 79 rrc(a) dcd dce inverting output 30 loopback loopback mode enable input 80 gnd signal ground 31 txd txd driver ttl input 81 rs(a) rts inverting output 32 txce txce driver ttl input 82 vcc power supply input 33 st st driver ttl input 83 rs(b) rts non-inverting output 34 rts rts driver ttl input 84 gnd signal ground 35 dtr dtr driver ttl input 85 tr(a) dtr inverting output 36 dcd_dce dcd dce driver ttl input 86 vcc power supply input 37 rl rl driver ttl input 87 tr(b) dtr non-inverting output 38 ll ll driver ttl input 88 gnd signal ground 39 rxd rxd receiver ttl output 89 st(a) st inverting output 40 rxc rxc receiver ttloutput 90 vcc power supply input 41 txc txc receiver ttl output 91 st(b) st non-inverting output 42 cts cts receiver ttl output 92 gnd signal ground 43 dsr dsr receiver ttl output 93 tt(a) txce inverting output 44 dcd_dte dcd dte receiver ttl output 94 vcc power supply input 45 ri ri receiver ttl output 95 tt(b) txce non-inverting output 46 tm tm receiver ttl output 96 gnd signal ground 47 gnd signal ground 97 sd(a) txd inverting output 48 vcc power supply input 98 vcc power supply input 49 rd(b) rxd non-inverting input 99 sd(b) txd non-inverting output 50 rd(a) rxd inverting input 100 vcc power supply input
11 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation table 1. driver mode selection table 2. receiver mode selection SP3508 driver table SP3508 receiver table t u p t u o r e v i r d n i p e d o m 5 3 . v 0 3 5 - a i e e d o m 2 3 2 - s r e d o m ) 8 2 . v ( a 0 3 5 - a i e e d o m 9 4 4 - s r e d o m ) 6 3 . v ( e d o m 1 2 . x ) 1 1 . v ( n w o d t u h s d e t s e g g u s l a n g i s e d o m ) 2 d , 1 d , 0 d ( 1 0 00 1 01 1 00 0 11 0 10 1 11 1 1 t 1 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( d x t t 1 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( d x t t 2 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c x t t 2 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c x t t 3 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c d _ c x t t 3 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c d _ c x t t 4 ) a ( t u o8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( s t r t 4 ) b ( t u oz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( s t r t 5 ) a ( t u o8 2 . v1 1 . v8 2 . v0 1 . v1 1 . v1 1 . vz - h g i h) a ( r t d t 5 ) b ( t u oz - h g i h1 1 . vz - h g i hz - h g i h1 1 . v1 1 . vz - h g i h) b ( r t d t 6 ) a ( t u o8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c d _ d c d t 6 ) b ( t u oz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c d _ d c d t 7 ) a ( t u o8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hl r t 8 ) a ( t u o8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hl l t u p n i r e v i e c e r n i p e d o m 5 3 . v 0 3 5 - a i e e d o m 2 3 2 - s r e d o m ) 8 2 . v ( a 0 3 5 - a i e e d o m 9 4 4 - s r e d o m ) 6 3 . v ( e d o m 1 2 . x ) 1 1 . v ( n w o d t u h s d e t s e g g u s l a n g i s e d o m ) 2 d , 1 d , 0 d ( 1 0 00 1 01 1 00 0 11 0 10 1 11 1 1 r 1 ) a ( n i5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( d x r r 1 ) b ( n i5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( d x r r 2 ) a ( n i5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( c x r r 2 ) b ( n i5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( c x r r 3 ) a ( n i5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e t d _ c x t r 3 ) b ( n i5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e t d _ c x t r 4 ) a ( n i8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( s t c r 4 ) b ( n iz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( s t c r 5 ) a ( n i8 2 . v1 1 . v8 2 . v0 1 . v1 1 . v1 1 . vz - h g i h) a ( r s d r 5 ) b ( n iz - h g i h1 1 . vz - h g i hz - h g i h1 1 . v1 1 . vz - h g i h) b ( r s d r 6 ) a ( n i8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e t d _ d c d r 6 ) b ( n iz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e t d _ d c d r 7 ) a ( n i8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hi r r 8 ) a ( n i8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hm t
12 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 1. v.28 driver output open circuit voltage figure 2. v.28 driver output loaded voltage figure 3. v.28 driver output slew rate figure 4. v.28 driver output short-circuit current figure 6. v.28 driver output rise/fall times figure 5. v.28 driver output power-off impedance test circuits a v oc c a v t c 3k " a v t c 7k " oscilloscope scope used for slew rate measurement. a i sc c a c v cc = 0v 2v i x a c 3k " 2500pf oscilloscope
13 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 7. v.28 receiver input impedance figure 8. v.28 receiver input open circuit bias figure 9. v.10 driver output open-circuit voltage figure 10. v.10 driver output test terminated voltage figure 12. v.10 driver output power-off current figure 11. v.10 driver output short-circuit current a c i ia 15v a c v oc a v oc 3.9k " c a v t 450 " c a i sc c a c 0.25v v cc = 0v i x
14 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 13. v.10 driver output transition time figure 14. v.10 receiver input current figure 15. v.10 receiver input iv graph figure 16. v.11 driver output open-circuit voltage figure 17. v.11 driver output test terminated voltage figure 18. v.11 driver output short-circuit current a 450 " c oscilloscope a c i ia 10v a b v oc 3.9k " v oca v ocb c a b v t 50 " v os c 50 " a b c i sa i sb v .10 receiver +3.25ma -3.25ma +3v +10v -3v -10v maximum input current v ersus voltage
15 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 19. v.11 driver output power-off current figure 20. v.11 receiver input current figure 21. v.11 driver output rise/fall time figure 22. v.11 receiver input iv graph a b c i xa 0.25v a b c i xb 0.25v v cc = 0v v cc = 0v a b c i ia 10v c i ib 10v a b a b 50 " c 50 " 50 " v e oscilloscope v. 11 receiver +3.25ma -3.25ma +3v +10v -3v -10v maximum input current v ersus voltage
16 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 23. v.11 receiver input current w/ termination figure 24. v.11 receiver input graph with termination figure 25. v.35 driver output test terminated voltage figure 26. v.35 driver output source impedance a b c i ia 6v c i ib 6v a b 100 " to 150 " 100 " to 150 " a b v 2 50 " c 24khz, 550mv p-p sine wave v 1 a b 50 " c 50 " v t v os v. 11 receiver w/ optional cable termination (100 " to 150 " ) i [ma] = v [v] / 0.1 i [ma] = v [v] - 3) / 4.0 i [ma] = v [v] / 0.1 i [ma] = v [v] - 3) / 4.0 -6v -3v +3v +6v maximum input current versus voltage figure 27. v.35 driver output short-circuit impedance a b c i sc 2v
17 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 31. driver output leakage current test figure 32. driver/receiver timing test circuit figure 29. v.35 receiver input source impedance figure 28. v.35 driver output rise/fall time figure 30. v.35 receiver input short-circuit impedance a b c 50 " oscilloscope 50 " 50 " a b v 2 50 " c 24khz, 550mv p-p sine wave v 1 a b c i sc 2v a b i zsc logic ?1? 10v 11 1 d 2 d 1 d 0 v cc = 0v v cc any one of the three conditions for disabling the driver. i zsc 10v c l1 15pf r out b a b a t in c l2 f in (50% duty cycle, 2.5v p-p )
18 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 33. driver timing test load circuit figure 34. receiver timing test load circuit figure 35. driver propagation delays figure 36. driver enable and disable times figure 37. receiver propagation delays 500 " c l output under t est s 1 s 2 v cc 1k " 1k " c rl receiver output s 1 s 2 t est point v cc +3v 0v 5v v ol a, b 0v 1.5v 1.5v t zl t zh v oh a, b 2.3v 2.3v t lz t hz 0.5v 0.5v output normally low output normally high mx or tx_enable f = 1mhz; t r # 10ns; t f # 10ns v oh v ol receiver out (v oh - v ol )/2 (v oh - v ol )/2 t plh f > 10mhz; t r < 5ns; t f < 5ns output v 0d2 + v 0d2 ? a ? b 0v 0v t phl input t skew = | t phl - t plh | +3v 0v driver input a b driver output v o + differential output v b ? v a 0v v o ? 1.5v 1.5v t plh t r t f f > 10mhz; t r < 5ns; t f < 5ns v o 1/2v o 1/2v o t phl t dplh t dphl t skew = | t dplh - t dphl |
19 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 38. receiver enable and disable times figure 39. v.28 (rs-232) and v.10 (rs-423) driver enable and disable times +3v 0v tx_enable 1.5v 1.5v t zl f = 60khz; t r < 10ns; t f < 10ns t out t lz output low 0v +3v 0v v oh 1.5v 1.5v t zh f = 60khz; t r < 10ns; t f < 10ns t out t hz output high 0v tx_enable v ol 0.5v v oh - v ol 0.5v - v ol 0.5v - +3v 0v +3.3v receiver out 0v 1.5v 1.5v t zl t zh f = 1mhz; t r < 10ns; t f < 10ns receiver out 1.5v 1.5v t lz t hz 0.5v 0.5v output normally low output normally high v il v ih decx rx enable
20 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 40. typical v.10 driver output waveform. figure 41. typical v.11 driver output waveform. figure 42. typical v.28 driver output waveform. figure 43. typical v.35 driver output waveform.
21 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 44. functional diagram txd sd(a) sd(b) sden v cc v dd c1- c1+ +3.3v (decoupling capacitor not shown) 1 f SP3508 txce tt(a) tt(b) tten st st(a) st(b) sten rd(a) rxd rden rd(b) r t(a) rxc r ten r t(b) txc(a) txc txcen txc(b) cs(a) cts csen cs(b) dm(a) dsr dmen dm(b) rrt(a) dcd_dte rrten rrt(b) tm(a) tm tmen rts rs(a) rs(b) rsen dtr tr(a) tr(b) tren dcd_dce rrc(a) rrc(b) rrcen ll ll(a) llen c2- c2+ 1 f 1 f gnd d0 d1 d2 term-off d-latch v .10-gnd rl rl(a) rlen ic ri icen loopback 76 29 50 39 10 49 52 40 11 51 55 41 12 53 57 42 14 56 59 43 13 58 62 44 15 61 63 45 16 64 46 17 18 19 20 21 22 30 +3.3v (s ee p i nout ass i gnments f or gnd and v cc pins) 74 70 72 69 agnd 31 97 99 2 32 93 95 3 33 89 91 4 34 81 83 6 35 85 87 5 36 79 77 7 37 67 8 38 65 9 60 28 v .35 mode rx enable 51ohms 51ohms 124ohms receiver termination network v .11 mode v .35 mode tx enable 51ohms 51ohms 124ohms v .35 driver termination network v ss1 68 v ss2 1 f 27 1 f 1 f 24 26 av cc c3- c3+ inverter regulated charge pump c vdd c1 c2 c3 c vss1 c vss2
22 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation the SP3508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. the SP3508 offers the hardware interface modes for rs-232 (v.28), rs-449/v.36 (v.11 and v.10), eia-530 (v.11 and v.10), eia-530a (v.11 and v.10), v.35 (v.35 and v.28) and x.21(v.11). the interface mode selection is done via three control pins, which can be latched via micropro- cessor control. the SP3508 has eight drivers, eight receivers, and sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail- safe when inputs are either open or shorted. theory of operation the SP3508 device is made up of 1) the drivers 2) the receivers 3) charge pumps 4) dte/dce switching algorithm 5) control logic. drivers the SP3508 has eight enhanced independent drivers. control for the mode selection is done via a three-bit control word into d0, d1, and d2. the drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accom- modate the selected interface mode. as the mode of the drivers is changed, the electrical characteristics will change to support the re- quired signal levels. the mode of each driver in the different interface modes that can be se- lected is shown in table 1. there are four basic types of driver circuits itu-t-v.28 (rs-232), itu-t-v.10 (rs-423), itu-t-v.11 (rs-422), and ccitt-v.35. the v.28 (rs-232) drivers output single-ended signals with a minimum of +5v (with 3k " & 2500pf loading), and can operate over 120kbps. since the SP3508 uses a charge pump to gener- ate the rs-232 output rails, the driver outputs will never exceed +10v. the v.28 driver archi- tecture is similar to sipex's standard line of rs- 232 transceivers. the rs-423 (v.10) drivers are also single-ended signals which produce open circuit v ol and v oh measurements of +4.0v to +6.0v. when terminated with a 450 " load to ground, the driver output will not deviate more than 10% of the open circuit value. this is in compliance of the itu v.10 specification. the v.10 (rs-423) drivers are used in rs-449/v.36, eia-530, and eia-530a modes as category ii signals from each of their corresponding specifications. the v.10 driver can transmit over 120kbps if neces- sary. the third type of drivers are v.11 (rs-422) differential drivers. due to the nature of differ- ential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. the advantage is evident over high speeds and long transmission lines. the strength of the driver outputs can produce differential signals that can maintain +2v differential out- put levels with a load of 100 " . the strength allows the SP3508 differential driver to drive over long cable lengths with minimal signal degradation. the v.11 drivers are used in rs- 449, eia-530, eia-530a and v.36 modes as category i signals which are used for clock and data. sipex's new driver design over its prede- cessors allow the SP3508 to operate over 20mbps for differential transmission. features
23 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation the fourth type of drivers are v.35 differential drivers. there are only three available on the SP3508 for data and clock (txd, txce, and txc in dce mode). these drivers are current sources that drive loop current through a differential pair resulting in a 550mv differential voltage at the receiver. these drivers also incorporate fixed termination networks for each driver in order to set the v oh and v ol depending on load conditions. this termination network is basically a ? configuration consisting of two 51 " resistors connected in series and a 124 " resistor connected between the two 50 " resistors to gnd. filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. the drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable dte/dce. the enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on figure 44 . the enable pins have internal pull-up and pull- down devices, depending on the active polarity of the receiver, that enable the driver upon power- on if the enable lines are left floating. during disabled conditions, the driver outputs will be at a high impedance 3-state. the driver inputs are both ttl or cmos compatible. all driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic low (??. unused driver inputs can be left floating. the internal pull-up resistor value is approximately 500k " . receivers the SP3508 has eight enhanced independent receivers. control for the mode selection is done via a three-bit control word that is the same as the driver control word. therefore, the modes for the drivers and receivers are identical in the application. like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. as the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. table 1 shows the mode of each receiver in the different interface modes that can be selected. there are two basic types of receiver circuits?tu-t-v .28 (rs-232) and itu-t-v.11, (rs-422). the rs-232 (v.28) receiver is single-ended and accepts rs-232 signals from the rs-232 driver. the rs-232 receiver has an operating input voltage range of +15v and can receive signals downs to +3v. the input sensitivity complies with rs-232 and v.28 at +3v. the input impedance is 3k " to 7k " in accordance to rs- 232 and v.28. the receiver output produces a ttl/cmos signal with a +2.4v minimum for a logic ??and a +0.4v maximum for a logic ?? the rs-232 (v.28) protocol uses these receivers for all data, clock and control signals. they are also used in v.35 mode for control line signals: cts, dsr, ll, and rl. the rs-232 receivers can operate over 120kbps. the second type of receiver is a differential type that can be configured internally to support itu-t-v.10 and ccitt-v.35 depending on its input conditions. this receiver has a typical input impedance of 10k " and a differential threshold of less than +200mv, which complies with the itu-t-v.11 (rs-422) specifications. v.11 receivers are used in rs-449/v.36, eia-530, eia-530a and x.21 as category i signals for receiving clock, data, and some control line signals not covered by category ii v.10 circuits. the differential v.11 transceiver has improved architecture that allows over 20mbps transmission rates. receivers dedicated for data and clock (rxd, rxc, txc) incorporate internal termination for v.11. the termination resistor is typically 120 " connected between the a and b inputs. the termination is essential for minimizing crosstalk and signal reflection over the transmission line . the minimum value is guaranteed to exceed 100 " , thus complying with the v.11 and rs-422 specifications. this resistor is invoked when the receiver is operating as a v.11 receiver, in modes eia-530, eia-530a, rs-449/v.36, and x.21. features
24 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation the same receivers also incorporate a termination network internally for v.35 applications. for v.35, the receiver input termination is a ? termination consisting of two 51 " resistors connected in series and a 124 " resistor connected between the two 50 " resistors and gnd. the receiver itself is identical to the v.11 receiver. the differential receivers can be configured to be itu-t-v.10 single-ended receivers by internally connecting the non-inverting input to ground. this is internally done by default from the decoder. the non-inverting input is rerouted to v10gnd and can be grounded separately. the itu-t-v.10 receivers can operate over 120kbps and are used in rs-449/v.36, e1a- 530, e1a-530a and x.21 modes as category ii signals as indicated by their corresponding specifications. all receivers include an enable/ disable line for disabling the receiver output allowing convenient half-duplex configurations. the enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on figure 44 . the receiver? enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. during disabled conditions, the receiver outputs will be at a high impedance state. if the receiver is disabled any associated termination is also disconnected from the inputs. features all receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. for single-ended v.28 and v.10 receivers, there are internal 5k " pull-down resistors on the inputs which produces a logic high (?? at the receiver outputs. the differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic high (?? at the receiver output. charge pump SP3508 uses an internal capacitive charge pump to generate vdd and vss. the design is sipex patented (5,306,954) four-phased voltage shift- ing charge pump converters that converts the input voltage of 3.3v to nominal output volt- ages of +/-6v (vdd & vss1). SP3508 also in- cludes an inverter block that inverts vcc to -vcc (vss2). there is a free-running oscillator that controls the four phases of the voltage shifting. a description of each phase follows. 4-phased doubler pump phase 1 -v ss1 charge storage -during this phase of the clock cycle, the positive side of capacitors c1 and c2 are initially charged to v cc . c1+ is then switched to ground and the charge in c1- is transferred to c2-. since c2+ is connected to v cc , the voltage potential across capacitor c2 is now 2xv cc . v cc = +3v ?3v ?3v +3v v ss1 storage capacitor v dd storage capacitor c 1 c 2 + + ++ ? ? ? ? c vdd c vss1 figure 45. charge pump - phase 1.
25 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation phase 2 -v ss1 transfer -phase two of the clock connects the negative terminal of c2 to the v ss1 storage capacitor and the positive terminal of c2 to ground, and transfers the negative generated voltage to c vss1 . this generated voltage is regulated to -5.5v. simultaneously, the positive side of the capacitor c1 is switched to v cc and the negative side is connected to ground. features phase 3 -v dd charge storage -the third phase of the clock is identical to the first phase-the charge transferred in c1 produces -v cc in the negative terminal of c1 which is applied to the negative side of the capacitor c2. since c2+ is at v cc , the voltage potential across c2 is 2xv cc . v cc = +3v ?6v v ss storage capacitor v dd storage capacitor c 1 c 2 + + ++ ? ? ? ? c vdd c vss1 figure 46. charge pump - phase 2. v cc = +3v ?3v +3v ?3v v ss1 storage capacitor v dd storage capacitor c 1 c 2 + + ++ ? ? ? ? c vss1 c vdd figure 47.charge pump - phase 3. phase 4 -v dd transfer -the fourth phase of the clock connects the negative terminal of c2 to ground, and transfers the generated 5.5v across c2 to c vdd , the v dd storage capacitor. this voltage is regulated to +5.5v. at the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor c1 is switched to v cc and the negative side is connected to ground, and the cycle begins again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. since both v+ and v- are separately generated from v cc ; in a no-load condition v+ and v- will be symmetrical. older charge pump approaches that generate v- from v+ will show a decrease in the magnitude of v- compared to v+ due to the inherent inefficiencies in the design. the clock rate for the charge pump typically operates at 250khz. the external capacitors can be as low as 1 f with a 16v breakdown voltage rating.
26 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation v cc = +3v +6v v ss1 storage capacitor v dd storage capacitor c 1 c 2 + + ++ ? ? ? ? c vdd c vss1 figure 48. charge pump - phase 4. 2-phased inverter pump phase 1 please refer to figure below: in the first phase of the clock cycle, switches s2 and s4 are opened and s1 and s3 closed. this connects the flying capacitor, c3, from vin to ground. c3 charge up to the input voltage applied at vcc. phase 2 in the second phase of the clock cycle, switches s2 and s4 are closed and s1 and s3 are opened. this connects the flying capacitor, c3, in parallel with the output capacitor, c vss2 . the charge stored in c3 is now transferred to c vss2 . simultaneously, the negative side of c vss2 is connected to v ss2 and the positive side is connected to ground. with the voltage across c vss2 smaller than the voltage across c3, the charge flows from c3 to c vss2 until the voltage at the v ss2 equals -v cc . c 3 s 2 s 1 s 3 s 4 v ss2 c vss2 + + v cc v ss2 = -v cc figure 49. circuit for an ideal voltage inverter. features
27 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation recommended signals and port pin assignments pin number pin mnemonic circuit pin mnemonic pin number signal type mnemo nic db-25 pin(f) signal type mnemo nic db-25 pin(f) signal type mnemo nic db-37 pin(f) signal type mnemo nic m34 pin(f) signal type mnemo nic db-15 pin(f) 31 txd sd(a) 97 v.28 bb 3 v.11 bb(a) 3 v.11 rd(a) 6 v.35 104 r v.11 r(a) 4 2 sden sd(b) 99 v.11 bb(b) 16 v.11 rd(b) 24 v.35 104 t v.11 r(b) 11 32 txce tt(a) 93 v.28 dd 17 v.11 dd(a) 17 v.11 rt(a) 8 v.35 115 v v.11 b(a) 7** 3 tten tt(b) 95 v.11 dd(b) 9 v.11 rt(b) 26 v.35 115 x v.11 b(b) 14** 33 st st(a) 89 v.28 db 15 v.11 db(a) 15 v.11 st(a) 5 v.35 114 y v.11 s(a) 6 4 sten st(b) 91 v.11 db(b) 12 v.11 st(b) 23 v.35 114 aa v.11 s(b) 13 34 rts rs(a) 81 v.28 cb 5 v.11 cb(a) 5 v.11 cs(a) 9 v.28 106 d v.11 i(a) 5 5 rsen rs(b) 83 v.11 cb(b) 13 v.11 cs(b) 27 v.11 i(b) 12 35 dtr tr(a) 85 v.28 cc 6 v.11 cc(a) 6 v.11 dm(a) 11 v.28 107 e 6 tren tr(b) 87 v.11 cc(b) 22 v.11 dm(b) 29 36 dcd_dce rrc(a) 79 v.28 cf 8 v.11 cf(a) 8 v.11 rr(a) 13 v.28 109 f 7 rrcen rrc(b) 77 v.11 cf(b) 10 v.11 rr(b) 31 37 rl rl(a) 67 v.28 ce 22 v.28 125 j 8rle n 38 ll ll(a) 65 v.28 tm 25 v.10 tm 25 v.10 tm 18 v.28 142 nn 9 llen# 39 rxd rd(a) 50 v.28 ba 2 v.11 ba(a) 2 v.11 sd(a) 4 v.35 103 p v.11 t(a) 2 10 rden# rd(b) 49 v.11 ba(b) 12 v.11 sd(b) 22 v.35 103 s v.11 t(b) 9 40 rxc rt(a) 52 v.28 da 24 v.11 da(a) 24 v.11 tt(a) 17 v.35 113 u v.11 x(a) 7** 11 rten# rt(b) 51 v.11 da(b) 11 v.11 tt(b) 35 v.35 113 w v.11 x(b) 14** 41 txc txc(a) 55 12 txcen# txc(b) 53 42 cts cs(a) 57 v.28 ca 4 v.11 ca(a) 4 v.11 rs(a) 7 v.28 105 c v.11 c(a) 3 13 csen# cs(b) 56 v.11 ca(b) 19 v.11 rs(b) 25 v.11 c(b) 10 43 dsr dm(a) 59 v.28 cd 20 v.11 cd(a) 20 v.11 tr(a) 12 v.28 108 h 14 dmen# dm(b) 58 v.11 cd(b) 23 v.11 tr(b) 30 44 dcd_dte rrt(a) 62 15 rrten# rrt(b) 61 45 ri ic 63 v.28 rl 21 v.10 rl 21 v.10 rl 14 v.28 140 n 16 icen# 46 tm tm(a) 64 v.28 ll 18 v.10 ll 18 v.10 ll 10 v.28 141 l 17 tmen SP3508 multiprotocol configured as dce interface to system logic interface to port- connector receiver_4 receiver_5 receiver_6 driver_7 driver_8 rs-449 v.35 x.21 driver_1 rs-232 or v.24 eia-530 receiver_2 receiver_3 driver_2 driver_3 driver_4 driver_5 receiver_1 driver_6 spare drivers and receivers may be used for optional signals (signal quality, rate detect, standby) or may be disabled using individual enable pins for each driver and receiver ** x.21 use either b() or x(), not both pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations receiver_7 receiver_8 dce configuration date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiv er ? copyright 2004 sipex corporation 27
28 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation recommended signals and port pin assignments pin number pin mnemonic circuit pin mnemonic pin number signal type mnemo nic db-25 pin(m) signal type mnemo nic db-25 pin(m) signal type mnemo nic db-37 pin(m) signal type mnemo nic m34 pin(m) signal type mnemo nic db-15 pin(m) 31 txd sd(a) 97 v.28 ba 2 v.11 ba(a) 2 v.11 sd(a) 4 v.35 103 p v.11 t(a) 2 2 sden sd(b) 99 v.11 ba(b) 12 v.11 sd(b) 22 v.35 103 s v.11 t(b) 9 32 txce tt(a) 93 v.28 da 24 v.11 da(a) 24 v.11 tt(a) 17 v.35 113 u v.11 x(a) 7** 3 tten tt(b) 95 v.11 da(b) 11 v.11 tt(b) 35 v.35 113 w v.11 x(b) 14** 33 st st(a) 89 4 sten st(b) 91 34 rts rs(a) 81 v.28 ca 4 v.11 ca(a) 4 v.11 rs(a) 7 v.28 105 c v.11 c(a) 3 5 rsen rs(b) 83 v.11 ca(b) 19 v.11 rs(b) 25 v.11 c(b) 10 35 dtr tr(a) 85 v.28 cd 20 v.11 cd(a) 20 v.11 tr(a) 12 v.28 108 h 6 tren tr(b) 87 v.11 cd(b) 23 v.11 tr(b) 30 36 dcd_dce rrc(a) 79 7 rrcen rrc(b) 77 37 rl rl(a) 67 v.28 rl 21 v.10 rl 21 v.10 rl 14 v.28 140 n 8rle n 38 ll ll(a) 65 v.28 ll 18 v.10 ll 18 v.10 ll 10 v.28 141 l 9ll en# 39 rxd rd(a) 50 v.28 bb 3 v.11 bb(a) 3 v.11 rd(a) 6 v.35 104 r v.11 r(a) 4 10 rden# rd(b) 49 v.11 bb(b) 16 v.11 rd(b) 24 v.35 104 t v.11 r(b) 11 40 rxc rt(a) 52 v.28 dd 17 v.11 dd(a) 17 v.11 rt(a) 8 v.35 115 v v.11 b(a) 7** 11 rten# rt(b) 51 v.11 dd(b) 9 v.11 rt(b) 26 v.35 115 x v.11 b(b) 14** 41 txc txc(a) 55 v.28 db 15 v.11 db(a) 15 v.11 st(a) 5 v.35 114 y v.11 s(a) 6 12 txcen# txc(b) 53 v.11 db(b) 12 v.11 st(b) 23 v.35 114 aa v.11 s(b) 13 42 cts cs(a) 57 v.28 cb 5 v.11 cb(a) 5 v.11 cs(a) 9 v.28 106 d v.11 i(a) 5 13 csen# cs(b) 56 v.11 cb(b) 13 v.11 cs(b) 27 v.11 i(b) 12 43 dsr dm(a) 59 v.28 cc 6 v.11 cc(a) 6 v.11 dm(a) 11 v.28 107 e 14 dmen# dm(b) 58 v.11 cc(b) 22 v.11 dm(b) 29 44 dcd_dte rrt(a) 62 v.28 cf 8 v.11 cf(a) 8 v.11 rr(a) 13 v.28 109 f 15 rrten# rrt(b) 61 v.11 cf(b) 10 v.11 rr(b) 31 45 ri ic 63 v.28 ce 22 v.28 125 j 16 icen# 46 tm tm(a) 64 v.28 tm 25 v.10 tm 25 v.10 tm 18 v.28 142 nn 17 tmen rs-449 v.35 x.21 receiver_7 receiver_8 rs-232 or v.24 eia-530 receiver_4 receiver_5 receiver_6 driver_7 driver_8 driver_6 driver_2 driver_3 driver_4 driver_5 spare drivers and receivers may be used for optional signals (signal quality, rate detect, standby) or may be disabled using individual enable pins for each driver and receiver ** x.21 use either b() or x(), not both pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations SP3508 multiprotocol configured as dte interface to system logic interface to port- connector driver_1 receiver_1 receiver_2 receiver_3 dte configuration date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiv er ? copyright 2004 sipex corporation 28
29 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation term_off function the SP3508 contains a term_off pin that dis- ables all three receiver input termination networks regardless of mode. this allows the device to be used in monitor mode applications typically found in networking test equipment. the term_off pin internally contains a pull- down device with an impedance of over 500k " , which will default in a "on" condition during power-up if v.35 receivers enable line and the shutdown mode from the decoder will disable the termination regardless of term_off. loopback function the SP3508 contains a loopback pin that invokes a loopback path. this loopback path is illustrated in figure 50. loopback has an inter- nal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. during loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. decoder and d_latch function the SP3508 contains a d_latch pin that latches the data into the d0, d1 and d2 decoder inputs. if tied to a logic low ("0"), the latch is transparent, allowing the data at the decoder inputs to propa- gate through and program the SP3508 accord- ingly. if tied to a logic high ("1"), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic low. features there are internal pull-up devices on d0, d1 and d2, which allow the device to be in shutdown mode ("111") upon power up. however, if the device is powered-up with the d_latch at a logic high, the decoder state of the SP3508 will be undefined. ctr1/ctr2 european compliancy as with all of sipex's previous multi-protocol serial transceiver ic's the drivers and receivers have been designed to meet all the requirements to net1/net2 and tbr2 in order to meet ctr1/ ctr2 compliancy. the SP3508 is also tested in- house at sipex and adheres to all the net1/2 physical layer testing and the itu series v speci- fications before shipment. please note that al- though the SP3508, as with its predecessors, ad- here to crt1/ctr2 compliancy testing, any com- plex or usual configuration should be double- checked to ensure ctr1/ctr2 compliance. con- sult the factory for details.
30 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 50. loopback path sd(a) sd(b) rd(a) rd(b) tt(a) tt(b) r t(a) r t(b) txd rxd txce rxc st(a) st(b) txc(a) txc(b) st txc rs(a) rs(b) cs(a) cs(b) tr(a) tr(b) dm(a) dm(b) rts cts dtr dsr rrc(a) rrc(b) rrt(a) rrt(b) dcd_dce dcd_dte rl(a) ic rl ri ll(a) tm(a) ll tm 31 39 32 40 33 41 34 42 35 43 36 44 37 45 38 46 97 99 50 49 93 95 52 51 89 91 55 53 81 83 57 56 85 87 59 58 79 77 62 61 67 63 65 64
31 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation figure 51. SP3508 typical operating configuration to serial port connector with dce/dte programmability 20 (v.11, v.28) dtr_dsr_a 23 (v.11) dtr_dsr_b 1 f 1 f c vdd v cc v dd c1- c2- c1+ c2+ 1 f SP3508cf txd txce st rts dtr dcd_dce rl rxc txc cts dsr dcd_dte ri tm 10 f db-26 serial port connector pins signal (dte_dce) 2 (v.11, v.35, v.28) txd_rxd_a 14 (v.11, v.35) txd_rxd_b 11 (v.11, v.35) txce_txc_b 25 (v.10, v.28) ll_tm 15 (v.11, v.35, v.28) *txc_rxc_a 12 (v.11, v.35) *txc_rxc_b sden 24 (v.11, v.35, v.28) txce_txc_a 3 (v.11, v.35, v.28) rxd_txd_a 16 (v.11, v.35) rxd_txd_b 8 (v.11, v.28) dcd_dcd_a 10 (v.11) dcd_dcd_b 9 (v.11, v.35) rxc_txce_b 17 (v.11, v.35, v.28) rxc_txce_a llen sten gnd * - driver applies for dce only on pins 15 and 12. receiver applies for dte only on pins 15 and 12. +3.3v i/o lines represented by double arrowhead signifies a bi-directional bus. input line output line ll rxd tten rsen tren rrcen rlen rden tmen txcen r ten csen dmen rrten icen term_off d_latch d0 d1 d2 charge pump section tr ansceiver section logic section +3.3v 21 (v.10, v.28) rl_ri 22 (v.10, v.28) ri_rl 18 (v.10, v.28) ll_tm dce/dte driver applies for dce only on pins 8 and 10. receiver applies for dte only on pins 8 and 10. loopback +3.3v 19 (v.11) rts_cts_b 4 (v.11, v.28) rts_cts_a 6 (v.11, v.28) dsr_dtr_a 22 (v.11) dsr_dtr_b 13 (v.11) cts_rts_b 5 (v.11, v.28) cts_rts_a 31 sd(a) 35 34 38 39 40 42 43 44 41 32 36 45 37 46 agnd sd(b) tt(a) tt(b) st(a) st(b) rs(a) rs(b) tr(a) tr(b) rrc(a) rrc(b) rl(a) rd(a) ll(a) rd(b) r t(a) r t(b) txc(a) txc(b) cs(a) cs(b) dm(a) dm(b) rrt(a) rrt(b) ic tm(a) 18 19 20 97 99 93 95 89 91 81 83 85 87 79 77 67 50 65 49 51 55 53 57 56 59 58 62 61 63 64 52 21 22 30 28 +3.3v av cc 24 26 68 27 v ss2 v ss1 c3+ c3- 69 72 70 74 76 29 1 f c1 c2 c3 c vss1 c vss2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 33
32 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation package: 100 pin lqfp 100 pin lqfp pin 1 e1 d1 d c l b e seating plane a1 c l e a l 11 -13 0 min 0 ?7 0.2 rad max. 0.08 rad min. dimensions minimum/maximum (mm) symbol a a1 a2 b d d1 e e e1 n 100?pin lqfp jedec ms-026 (bed) variation min nom max 1.60 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27 16.00 bsc 14.00 bsc 0.50 bsc 16.00 bsc 14.00 bsc 100 a c l1 a2 11 -13 common dimensions symbl min nom max c 0.09 0.20 l 0.45 0.60 0.75 l1 1.00 ref
33 date: 06/14/04 SP3508 enhanced wan multi?mode serial transceiver ? copyright 2004 sipex corporation ordering information part number temperature range package types SP3508cf ............................................. 0 c to +70 c ................................................. 100?pin jedec lqfp SP3508ef ......................................... -40 c to +85 c ................................................. 100?pin jedec lqfp corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 revision history available in lead free packaging. to order add ?-l? suffix to part number. example: SP3508ef = standard; SP3508ef-l = lead free date revision description 1/12/04 a implemented tracking revision. 2/27/04 b included diamond column in spec table indicating which specs apply over full operating temp. range. in figure 51, fixed typo on pin 61 and 62 from an input line to a bidirectional bus. 3/31/04 c corrected max dimension for symbol c on lqfp package. 6/3/04 d added tables to page 27 and 28.

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